Field
The disclosed technology relates to semiconductor technology, and particularly to a FinFET and methods of manufacturing the same.
Description of the Related Technology
As planar semiconductor devices scale down, short-channel effects become increasingly significant. In order to address such problems, three-dimensional semiconductor devices such as fin field effect transistors (FinFETs) have been proposed. Generally, a FinFET includes a semiconductor fin in which a channel region may be formed, and a gate stack covering at least one sidewall of the fin. The gate stack intersects the fin, and includes a gate conductor and a gate dielectric. The gate dielectric isolates the gate conductor from the fin. The FinFET may have a double-gate, tri-gate, or annular-gate configuration. The fin has a small width (i.e., thickness), and thus the FinFET may improve control of carriers in the channel region by the gate conductor, and suppress short-channel effects.
A conventional process for manufacturing the gate stack includes depositing a dielectric layer and a conductor layer, and then patterning the gate stack by photolithography. However, as the size of devices decreases, it is increasingly difficult to form a gate of small size (i.e., length) in a length direction of the semiconductor fin. Therefore, there is a need for methods of manufacturing semiconductor devices including FinFETs with small gate sizes.